The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Typically, magnetic recording channel systems employ error correction codes (ECC) (e.g., 12-bit Reed Solomon (RS) code) to remove residual errors made by the channel detector. Error detection codes (EDC) are used to detect decoding failure produced by the ECC. After data encoded by the ECC and EDC is read from a storage medium, the data is decoded using an ECC decoder. The ECC decoder produces an error polynomial which is checked by EDC circuitry to detect failure in the error correction. However, the error polynomial produced by the ECC decoder is in reverse order from normal order in which the data is read from the storage medium. Moreover, because the EDC circuitry typically operates on the data in this normal order, traditional systems lack efficient techniques for processing the error polynomial produced by the ECC decoder.